JEDEC has released a series of industry standards for interconnection between a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC) and logic devices using serial data lanes. Some of these industry standards, for example, the JESD204B serial interface specification, support multiple data lanes in parallel (e.g., 4 lanes between an ADC and a logic device) but require that the skew between serial lanes be kept within specified tolerances.
In an ADC or DAC integrated circuit (IC) chip, for most digital blocks, latency is consistent due to the nature of digital processing. However, a first in first out (FIFO) buffer typically is used at the end of a data path for the digital blocks to transfer a bitstream from a digital clock domain to a high frequency analog serial clock domain. The design of the FIFO is complicated due to the high frequency nature of the encoding scheme and high-speed nature of the serial link. For example, the JESD204B serial interface uses an “8b10b” encoding scheme that converts an 8-bit value into a 10-bit code, with some redundancy for control codes. Under this encoding scheme, a framer circuit, which creates properly encoded frames, produces a multiple number of 10-bit codes per write clock period. At the other side of the buffer, it is possible to design a serializer that could handle input-output ratios that are not a power of two (2). However, this is more complex than the power of 2 version and more difficult to achieve the required speed. Thus, high speed analog circuits that serialize the bitstream typically operate on a power of 2 basis. For example, the analog circuit of a two-channel 16-bit ADC reads 32 bits from a FIFO per read clock period while the digital domain writes 40 bits per write clock period. Thus, the read and write clocks for the FIFO are at different frequencies and have no defined phase relationship. This asynchronous nature of the write and read clocks to the FIFO causes the FIFO to have an inconsistent latency. In worst-case scenarios, this could lead to a variation in latency by up to one clock period. This would exceed the skew allowances in the specification.
Therefore, the inventor perceives a need in the art for an ADC or DAC chip with an alignment system that ensures a low variation in latency through parallel FIFOs.